1. Field of the Invention
This invention is related to processors, and more particularly, to a method and apparatus for fault handling during the execution of computer instructions.
2. Description of the Relevant Art
Superscalar microprocessors achieve high performance by executing multiple instructions concurrently and by choosing the shortest possible clock cycle consistent with the design. As used herein, the term xe2x80x9cclock cyclexe2x80x9d refers to an interval of time in which the various stages of the instruction processing pipelines complete their tasks. Instructions and computed values are captured by memory elements (such as registers or arrays) according to a clock signal defining the clock cycle. For example, a memory element may capture a value according to the rising or falling edge of the clock signal.
Many superscalar microprocessor manufacturers design their microprocessors in accordance with the x86 microprocessor architecture. The x86 microprocessor architecture is widely accepted in the computer industry, and therefore a large body of software exists which is designed to this architecture. Microprocessors designed in accordance with the x86 architecture advantageously retain compatibility with this body of software. As will be appreciated by those skilled in the art, the x86 architecture (as well as many other architectures) includes a xe2x80x9cstackxe2x80x9d area in memory. The stack is useful for passing information between a program and a subroutine called by that program, among other things. In the x86 architecture, a variety of architecturally defined (xe2x80x9carchitectedxe2x80x9d) registers are included for storing operands of instructions. For example, the ESP (extended stack pointer) register points to the address in memory which currently forms the top of the stack. A stack structure is a Last-In, First-Out (LIFO) structure in which values are placed on the stack in a certain order and are removed from the stack in the reverse order. Therefore, the top of the stack contains the last item placed on the stack. The action of placing a value on the stack is known as a xe2x80x9cpushxe2x80x9d, and requesting that a push be performed is a xe2x80x9cpush commandxe2x80x9d. The action of removing a value from the stack is referred to as a xe2x80x9cpopxe2x80x9d, and requesting that a pop be performed is a xe2x80x9cpop commandxe2x80x9d. When a push command is performed, the ESP register is decremented by the size (in bytes) of the value specified by the push command. The value is then stored at the address pointed to by the decremented ESP register value. When a pop command is performed, a number of bytes specified by the pop command are copied from the top of the stack to a destination specified by the pop command, and then the ESP register is incremented by the number of bytes.
Often times, an instruction (typically a microcode instruction) may include several operations, some of which may cause further updates to the ESP register. In addition to updating the ESP register, a microcode routine corresponding to one of such instructions may also include operations which allow the tracking of previous ESP register states should the routine need to be restarted in the event of a fault. Typically, an additional tracking operation may be added to a microcode routine for each update of the ESP register within the routine. The tracking of previous states of the ESP register may also involve writing such states to temporary storage locations, and reading from a temporary storage location if a previous ESP register value must be retrieved. Such operations may be performed each time the microcode routine containing them is executed. The adding of such extra operations may result in a performance penalty when executing the microcode routine without experiencing a fault, and may increase its complexity as well. This performance penalty may become severe for a complex microcode routine that involves several updates of the ESP register.
If a fault or an exception occurs, a microcode fault handler or other type of exception handler may execute fault handling routines. Such fault handling routines may attempt to remove those conditions from which the fault originated. Such fault handling routines may also attempt to restore the ESP register to its state just prior to the occurrence of the fault. The ability to restore the ESP register to its pre-fault state may be dependent upon the correct functioning of tracking operations in complex microcode routines. If such routines contain bugs or otherwise fail to properly track the updates of the ESP register, the currently running program may experience erroneous operation, and in some cases, may be prematurely terminated.
The problems outlined above are in large part solved by a method and apparatus for fault handling in computer systems. In one embodiment, a first register is used to store an address which points to the top of a stack. The address stored in the first register may be updated during the execution of an instruction. A second register may be used to store the address previously stored in the first register. The contents of the second register may be kept unchanged until the retirement of the instruction that is currently executing. If a fault occurs during execution of the instruction, a microcode fault handler may perform routines that may clear the fault or those conditions which led to the fault. The microcode fault handler may also copy the contents of the second register back into the first register. Execution of the instruction may be restarted from the operation just prior to when the fault occurred. The program from which the instruction originated may then continue to run. The first and second registers may be general-purpose registers in some embodiments, while special purpose registers may be used in other embodiments.
In one embodiment, the method and apparatus may be implemented in an x86 processor. The ESP register of an x86 processor may store an address which points to the top of a stack (often referred to as a stack pointer). The contents of a speculative ESP, which may be a register distinct from the ESP register, may be updated during the execution of an instruction (e.g. at the retirement of various instructions in a microcode routine corresponding to the instruction). The speculative ESP may correspond to an architected ESP register. A second register, known as a recovery ESP, may also store the address, and may not be updated until the currently executing instruction is retired (e.g. at the exit of the microcode routine).
A reorder buffer may be used to monitor the registers and make updates as necessary. If, during the execution of an instruction, the reorder buffer detects an update to the ESP register, it may also update the recovery ESP following the retirement of that instruction. The reorder buffer may also store previous updates of the ESP register. At least one address corresponding to an operation in a previous instruction may be maintained in the recovery ESP. If a fault occurs during the execution of the instruction, the reorder buffer may then copy the address from the beginning instruction boundary back to the speculative ESP, responsive to instructions from the microcode fault handler. If the microcode fault handler successfully clears the fault condition(s), execution of the instruction may resume from the beginning instruction boundary.
In general, the method and apparatus may be applied to any computer architecture which employs the use of a stack and a register which may be used to store a stack pointer. Furthermore, the method and apparatus may be applied to any register.
Thus, in various embodiments, the method and apparatus for fault handling may allow a computer system to recover from a fault. A second register may be used to store and maintain address updates from a first register, which may be used as a stack pointer. If the attempted execution of a given instruction results in a fault, a microcode fault handler may clear those conditions which caused the fault. An address stored in the second register may be copied back into the first register, returning the first register to its original state at the beginning of the instruction which faulted. Execution of the instruction may then be restarted. In many cases, the occurrence and handling of the fault may be transparent to a user of the computer system. The method and apparatus may prevent the crash of application or system software.
Furthermore, by using a hardware mechanism to store previous states of the first register, operations for tracking the various states of the first register may be eliminated from complex microcode routines. This may result in the elimination of the performance penalty associated with such tracking operations. In addition, a programmer of microcode instructions may be relieved of the task of programming extra operations to keep track of previous states of the ESP register, instead relying on hardware to accomplish this task. As such, complex microcode routines may operate more efficiently, and may be significantly easier to program.